A junction field-effect transistor (hereinafter referred to as JFET) has a pn junction provided on either side of a channel region where carriers flow through, and a reverse bias voltage is applied from a gate electrode to expand a depletion layer from the pn junction into the channel region, thereby controlling the conductance of the channel region to perform an operation such as switching. A lateral JFET which is one type of the JFET refers to the one in which carriers move in the channel region in parallel with the surface of the device.
The carriers in the channel may be electrons (n-type) or holes (p-type). Usually, most JFETs in which SiC is used for the semiconductor substrate include the channel region that is an n-type impurity region. Therefore, for convenience of the description below, it is supposed that carriers in the channel are electrons and thus the channel region is an n-type impurity region; however, it should be understood that the channel region is a p-type impurity region in some cases.
An example of such a lateral JFET is disclosed for example in Japanese Patent Laying-Open No. 2003-68762.
FIG. 14 is a schematic cross section showing a structure of a conventional lateral JFET disclosed in the above-referenced publication. Referring to FIG. 14, a p− epitaxial layer 103 is provided on an SiC single crystal substrate 101. On this p− epitaxial layer 103, an n-type epitaxial layer 104 having a higher impurity concentration than p− epitaxial layer 103 is provided. On this n-type epitaxial layer 104, a p-type epitaxial layer 109 is provided.
In this p-type epitaxial layer 109, an n+ source region 106 and an n+ drain region 107 having a higher impurity concentration than n-type epitaxial layer 104 are provided with a predetermined space therebetween. Further, between n+ source region 106 and n+ drain region 107, a p+ gate region 105 having a higher impurity concentration than n-type epitaxial layer 104 is provided.
On respective surfaces of p+ gate region 105, n+ source region 106 and n+ drain region 107, a gate electrode 112a, a source electrode 112b and a drain electrode 112c are provided respectively. On a lateral side of n+ source region 106, a p+ semiconductor layer 108 that reaches to p− epitaxial layer 103 is formed, and source electrode 112b is electrically connected to p+ semiconductor layer 108.
In this lateral JFET, p+ gate region 105 has its impurity concentration higher than that of n-type epitaxial layer 104. Thus, in the lateral JFET, a depletion layer is expanded toward the channel by applying a reverse bias voltage to the pn junction between p+ gate region 105 and n-type epitaxial layer 104. In the state where the depletion layer closes the channel, the current cannot flow through the channel to cause an OFF state. Therefore, the magnitude of the reverse bias voltage can be adjusted to control whether to allow the depletion layer to block the channel region or not. As a result, the reverse bias voltage between the gate and the source for example can be adjusted to control the ON and OFF states of the current.
Patent Document 1: Japanese Patent Laying-Open No. 2003-68762